Journals Information
Universal Journal of Electrical and Electronic Engineering Vol. 2(3), pp. 124 - 127
DOI: 10.13189/ujeee.2014.020305
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Low-Voltage CMOS Multiplier Circuit Based on the Translinear Principle
Behzad Ghanavati *, Enayatollah Taghavi Moghaddam
Sama Technical and Vocational Training College, Islamic Azad University, Mahshahr Branch, Mahshahr, Iran
ABSTRACT
In this paper, novel current-mode analog multiplier circuit based on a pair of voltage-translinear Loop is presented. The proposed circuit is designed in 0.18 碌m standard CMOS technology. Simulation result using HSPICE that verify the functionality of circuit with 1 V supply is presented. The circuit can find application in the implementation of wide range of analog systems, Fuzzy and Neural Network circuits.
KEYWORDS
Analog Processing Circuit, Translinear Loop, Squarer Circuit, Low Voltage, Multiplier
Cite This Paper in IEEE or APA Citation Styles
(a). IEEE Format:
[1] Behzad Ghanavati , Enayatollah Taghavi Moghaddam , "Low-Voltage CMOS Multiplier Circuit Based on the Translinear Principle," Universal Journal of Electrical and Electronic Engineering, Vol. 2, No. 3, pp. 124 - 127, 2014. DOI: 10.13189/ujeee.2014.020305.
(b). APA Format:
Behzad Ghanavati , Enayatollah Taghavi Moghaddam (2014). Low-Voltage CMOS Multiplier Circuit Based on the Translinear Principle. Universal Journal of Electrical and Electronic Engineering, 2(3), 124 - 127. DOI: 10.13189/ujeee.2014.020305.