Journals Information
Universal Journal of Electrical and Electronic Engineering Vol. 4(2), pp. 67 - 72
DOI: 10.13189/ujeee.2016.040204
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Investigation of Digital Signal Processing of High-speed DACs Signals for Settling Time Testing
Rokas Kvedaras 1, Vygaudas Kvedaras 1, Tomas Ustinavi膷ius 1,*, Audron臈 Kvedarien臈 2, Ri膷ardas Masiulionis 1
1 Faculty of Electronics, Vilnius Gediminas Technical University, Lithuania
2 Faculty of Business Management, Vilnius Gediminas Technical University, Lithuania
ABSTRACT
Filtering of the measurement signals using digital brick-wall comb filters in frequency domain developed by the authors and measurement of the settling times of DACs are discussed in this paper. Results of the investigations made have shown that digital brick-wall comb filters are capable of reducing noise level by 10 times while keeping measurement signal undistorted. Investigation of the developed settling time measurement algorithm has determined influence of the internal noise of the sampling converter, noise of the transmission line, ADC and other sources of noise to the settling time measurement errors. It has been proved that by using the earlier developed measurement converter and the proposed digital filtering of the DAC signal it is possible to measure settling times of 12-14 bit DACs.
KEYWORDS
Digital Signal Processing, Digital Brick-wall Comb Filter, Settling Time Measurement, DAC Settling Time
Cite This Paper in IEEE or APA Citation Styles
(a). IEEE Format:
[1] Rokas Kvedaras , Vygaudas Kvedaras , Tomas Ustinavi膷ius , Audron臈 Kvedarien臈 , Ri膷ardas Masiulionis , "Investigation of Digital Signal Processing of High-speed DACs Signals for Settling Time Testing," Universal Journal of Electrical and Electronic Engineering, Vol. 4, No. 2, pp. 67 - 72, 2016. DOI: 10.13189/ujeee.2016.040204.
(b). APA Format:
Rokas Kvedaras , Vygaudas Kvedaras , Tomas Ustinavi膷ius , Audron臈 Kvedarien臈 , Ri膷ardas Masiulionis (2016). Investigation of Digital Signal Processing of High-speed DACs Signals for Settling Time Testing. Universal Journal of Electrical and Electronic Engineering, 4(2), 67 - 72. DOI: 10.13189/ujeee.2016.040204.